The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technologies to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
These high performance designs require even higher performance verification. We are looking for Design Verification (DV) engineers who are passionate about writing testbenches and building verification environments to exercise complex HDL. You are excited about exploring the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.
Design verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.
Responsibilities
Qualifications
We do not allow multiple applications. Please apply to the ONE role you are most interested in and we will consider you for all open positions when reviewing your application.
The estimated base salary range for this position is 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance- based bonuses and a competitive benefits package.